1. Field of the Invention
This invention relates generally to processes for fabricating semiconductor transistors, and in particular to a new process for simultaneously forming raised sources and drains and interconnects for metal oxide semiconductor transistors.
2. Description of the Prior Art
Semiconductor devices are constantly being miniaturized. As the overall dimensions of semiconductor devices are made smaller and smaller, hundreds of thousands of integrated circuit (IC) components including metal oxide semiconductor field-effect transistors (MOSFETs) and other metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) components have to be packed into a single IC chip. Thus, it is not an overstatement that the semiconductor industry is constantly under pressure to improve device structure and processing methods so that new IC chips can meet ever-tightening functional requirements, e.g., compact size, high-speed operation, low operating voltage, and low power consumption.
The fabrication of field-effect transistors involves the formation of n-type and p-type doped regions. As the IC device components become smaller and smaller, the formation of very shallowly doped regions, i.e., "shallow junctions," becomes a major limiting factor in the fabrication of semiconductor devices having metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) components. Shallow junctions, when properly formed, can mitigate various undesirable effects caused by short channels, leakage current, contact resistance and sheet resistance.
Technical difficulties have plagued the formation of shallow junctions. For example, in the case of p junctions, the typical dopant is boron, which has a low atomic number (Z) of 5. On the one hand, during a conventional ion implantation process, low-Z dopant ions tend to channel through the crystalline structure of the semiconductor substrate and form an undesirable implantation profile with a deep tail, where the concentration and depth of the dopant ions easily extend beyond the desirable channel depth. On the other hand, low-energy ion implantation techniques (with energy less than 5 KeV) pose a separate set of problems: the size and direction of low-energy ion beams are difficult to control; low-energy ions tend to sputter, deposit or diffuse randomly instead of penetrating the substrate surface region; low-energy ion implanters are both difficult and expensive to make; and so on.
The use of raised source and drain has recently been proposed as an alternative way for forming a shallow junction in a semiconductor transistor. Thus, landing pads are first formed at the surface regions of the substrate where the source and the drain are to be formed; meanwhile, a resist mask protects the active region where the gate electrode is to be formed. Dopant ions are then implanted in the pads through a conventional ion implantation process. The implanted dopant ions are made to diffuse, typically by way of thermal treatment, into the designated substrate surface regions to form the raised source and drain. Subsequently, the protective resist mask is removed, and the gate electrode is formed at the active region. Various other elements of the semiconductor devices, such as the conductors and the dielectric layers, are sequentially formed on the substrate to complete the fabrication of the semiconductor transistor. Finally, interconnects are formed to link up the transistors and other IC components of the semiconductor device.
Although the inclusion of raised source and drain has made it possible to fabricate semiconductor transistors with shallow junctions, the constant miniaturization of semiconductor devices dictates that other improvements be made to both device structures and fabrication techniques relating to the formation of raised source and drain. First, as the lithographic line width is reduced to 0.25 .mu.m or smaller (i.e., deep submicron), it becomes more and more difficult to control the critical dimensions of the semiconductor devices through conventional exposure and etching schemes. Second, device miniaturization places great strain on device planarization requirements, particularly when such devices include raised sources and drains. Last but not the least, device miniaturization makes it increasingly difficult to avoid various problems associated with conventional interconnect-formation techniques, which typically form interconnect on top of the isolation regions of the IC device. Such interconnect problems include poor adhesion between interconnect and isolation layer and elevated interconnect resistance. In short, the mere use of raised source and drain taught in the conventional art is insufficient to cope with all the problems associated with the fabrication of ever-shrinking semiconductor devices. Accordingly, there is plenty of room for improvement in the fabrication of metal oxide semiconductor devices having raised source and drain electrodes.